github.com/xtofalex/naja ↗
Netlist API (and more) for EDA flow development
An animated visualization of xtofalex/naja's Git history from October 2021 to September 2022, built by 3 contributors. The codebase reached 2,724 lines, mostly Verilog. The video runs 45 seconds.
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Language
Verilog
Contributors
3
Lines of Code
2,724
From
2021-10-08
To
2022-09-14
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About xtofalex/naja
Naja is an open-source EDA framework for analyzing, optimizing, and transforming gate-level netlists in electronic design. It provides a complete pipeline from SystemVerilog parsing and elaboration through to netlist analysis and optimization, with outputs in both SNL interchange format and Verilog. The project is accessible through both Python and C++ APIs, making it suitable for tool developers and researchers working on chip design workflows.
The framework includes practical tools like naja_edit, a command-line utility for netlist optimization that performs dead logic elimination, constant propagation, and other transformations. Users can load synthesized designs with standard cells from Liberty libraries, navigate design hierarchies, perform connectivity analysis, and directly edit netlists through rename, reconnect, and deletion operations. The project provides six hands-on Jupyter notebooks covering topics from basic usage to analysis of real chips like the ibex RISC-V core, all runnable in Google Colab without local installation.
Naja is designed for the open-source semiconductor and EDA communities, with comprehensive documentation, a regression test suite, and active community support. It exposes two complementary internal representations—SNL for full read-write netlist operations and DNL for fast parallel analysis—allowing different use cases to be optimized appropriately. The project is supported by NLNet through the NGI0 Entrust Fund.
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