SinghCoder/Icarus_Verilog ↗
Created Feb 12, 2021 · View the SinghCoder/Icarus_Verilog repository page
This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum
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Contributors
4
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274
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Aug 21, 2019
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Dec 22, 2020
About SinghCoder/Icarus_Verilog
This repository contains a collection of Verilog code snippets and educational materials developed during the Computer Architecture course at BITS Pilani. The project serves as a learning resource with eight progressively complex lab exercises covering fundamental to advanced digital design concepts, from introductory Verilog syntax through combinational and sequential circuits, ALU design, register files, single-cycle and multi-cycle datapaths, and finally pipeline architecture.
The repository includes practical guidance on compiling and running Verilog code using Icarus Verilog, with instructions for both text-based output through monitor statements and graphical waveform visualization. Each lab is accompanied by a lab sheet, README notes, and corresponding Verilog implementations. The author has also documented common Verilog mistakes and syntax pitfalls that students frequently encounter, such as case sensitivity requirements, proper wire declarations, and correct module naming conventions.
While intended primarily as a personal course portfolio and study aid, the repository acknowledges that the code has not been thoroughly verified and may contain errors. The author explicitly states the materials are for educational purposes only and welcomes corrections through pull requests.
